Slew-Rate Enhanced Low-Dropout Regulator by Dynamic Current Biasing
نویسندگان
چکیده
منابع مشابه
An Enhanced Slew Rate Output Capacitor-free Low Dropout Regulator Based on Differential Transconductance Amplifier
A highly current-efficient and fast transient response capacitor-free low-dropout regulator (LDO) for Systemon-Chip (SoC) applications is presented in this paper. The proposed architecture is implemented using 0.35 μm CMOS technology. The proposed circuit is based on differential transconductance and push-pull amplifier. Common mode feedback (CMFB) resistors and direct voltage spike detection u...
متن کاملImproved Transient Response Capacitor-less Low Drop-out (LDO) Regulator using Current Mode Transconductance Amplifier and Slew Rate Enhancement Technique
This paper presents a capacitor-less low drop-out (LDO) regulator with current mode transconductance amplifier & slew-rate enhancement circuit. The proposed current mode transconductance amplifier as error amplifier improves the slew rate & slewrate enhancement circuit further senses the transient voltage at the output of the LDO to increase the bias current of the error amplifier for a short d...
متن کاملCapacitor-less Low Dropout Voltage Regulator
The study of power management techniques has increased drastically within the last few years corresponding to the vast increase in the use of portable, handheld battery applications. These power management systems typically contain several LDO voltage regulators that require large external capacitors. The large external capacitors can not be fully integrated in standard CMOS technologies and hi...
متن کاملAn Ultra-Low Quiescent Current CMOS Low-Dropout Regulator with Small Output Voltage Variations
An ultra-low quiescent current low-dropout regulator with small output voltage variations and improved load regulation is presented in this paper. It makes use of dynamically-biased shunt feedback as the buffer stage and the LDO regulator can be stable for all load conditions. The proposed structure also employs a momentarily current-boosting circuit to reduce the output voltage to the normal v...
متن کاملDesign and Simulation of Low Dropout Regulator
The proposed CMOS Low Dropout (LDO) regulator has been designed and simulated using TSMC 0.25μ CMOS process in cadence analog design environment . This paper illustrates the design criteria and corresponding analysis relevant to LDO. The experimental result shows that, it regulates an output voltage at 3.3V from a 3.5V supply, with a minimum dropout voltage of 200mV at a maximum output current ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Journal of electromagnetic engineering and science
سال: 2014
ISSN: 2234-8409
DOI: 10.5515/jkiees.2014.14.4.376